1. Field of the Invention
The present invention relates to a technology for analyzing a semiconductor integrated circuit, and particularly relates to a system and a method for analyzing crosstalk occurring in a semiconductor integrated circuit.
2. Description of the Related Art
As miniaturization of semiconductor integrated circuits progresses, crosstalk attributable to coupling capacitance between the wires has a significant influence on characteristics of the semiconductor integrated circuit. Specifically, malfunction of the semiconductor integrated circuit caused by crosstalk glitch, crosstalk delay and the like is a problem.
“Crosstalk glitch” is the phenomenon when a signal transition of a wire causes a pulse in an adjacent wire. “Signal transition” is the change of the signal level of the wire from a high level to a low level or the change from a low level to a high level. The wire affected by the crosstalk will be hereinafter referred to as a “victim”. The wire which causes the problem will be hereinafter referred to as an “aggressor”. “Crosstalk delay” is the phenomenon when the delay time of the signal level of the victim changes due to influence from the transition of the signal level of the aggressor when the signal levels of the aggressor and the victim change at the same time.
To analyze the crosstalk influence on characteristics of the semiconductor integrated circuit based on the design information of the semiconductor integrated circuit, a determination is made as to whether or not there is an overlapping of the timing windows between the wires, which are capacitance coupled with each other. “Timing window” refers to a period where the possibility of the signal level of wire transitioning exists. In other words, the timing window is defined as a time from the earliest time to the latest time when the signal level changes. In the case where two or more aggressors affect a single victim, the influence of the crosstalk caused by the crosstalk glitch may be largest when there is an overlapping of the timing windows of the aggressors, and the influence of the crosstalk caused by the crosstalk delay may be largest when there is an overlapping of the timing windows of the aggressors and the victim. In such case, it is necessary to investigate the crosstalk influence on characteristics of the semiconductor integrated circuit. In other words, by calculating the variable value of the delay time of the signal level caused by crosstalk delay (hereafter referred to as “crosstalk delay value”) or the size of the pulse that occurs due to crosstalk glitch, the crosstalk influence on characteristics of the semiconductor integrated circuit is analyzed.
The crosstalk delay value is a difference in delay time of the signal level between when crosstalk delay occurs and when crosstalk delay does not occur. For example, the crosstalk delay value is the difference between the delay time of the signal level of the victim when the signal level of the victim and aggressor change at the same time and the delay time of the victim when the signal level of the victim and aggressor do not change at the same time.
In the case of crosstalk glitch, the signal level of the victim is a constant value and it is necessary to consider the overlapping of the timing windows of a plurality of aggressors affecting the same victim. In the case of crosstalk delay, it is necessary to consider the timing window overlapping of the victim and a plurality of aggressors.
In general, in order to investigate whether or not there is the overlapping of the timing windows, the delay time of the signal level is calculated by analysis conditions. Signal delays in transistors, wires, and the like change according to the influence of temperature, power supply voltage, process dispersion, and the like.
As a result, for example, the timing window is calculated under condition in which the signal delay is a minimum and under condition in which the signal delay is a maximum, respectively. However, the timing window changes under the influence of temperature, power supply voltage, process dispersion, and the like. Therefore, it is not guaranteed that there is no overlapping of the timing windows under an analysis condition that is between the conditions that have been analyzed, even when the analyzed conditions indicate there is no overlapping of the timing windows.
To solve the above problem, there is a method to calculate the overlapping of the timing windows by changing, little by little, the analysis conditions of the temperature, power supply voltage, process dispersion and operating frequency of the semiconductor integrated circuit. By changing the analysis conditions, little by little, the possibility of overlooking the overlapping of timing windows is reduced. However, because it is necessary to investigate the timing windows after setting many analysis conditions, the time required to analyze the crosstalk is increased.